Environments

5. Environments#

Richie supports various development environments, depending on the implementation target.

5.1. Local Configuration File#

Create a local.cfg file at the root of the Richie repository and include the following fields:

  • TARGET_PLATFORM: Name of the target platform, which corresponds to the name field of a platform specification file;

  • BR2_RICHIE_BITSTREAM: Absolute path to the FPGA bitstream, included in the FPGA build of the target platform;

  • BR2_RICHIE_XSA: Absolute path to the XSA file, included in the FPGA build of the target platform.

This file must be updated everytime a field changes, e.g., when the FPGA should be configured with a different bitstream from the one specified by BR2_RICHIE_BITSTREAM.

5.2. List of Environments#

5.2.1. Accelerator Design #

Vivado HLS (Standard)

Description: HLS synthesis tested with the following setup.
Tool: Vivado HLS 2019.2 (Vitis HLS is also supported, but not tested for all accelerators).

Vitis HLS Vision Library

Description: HLS synthesis for Vitis HLS Vision accelerators.
Tool: Vitis HLS 2022.2.
Deps: Vitis Vision Library, OpenCV 4.4.0.
Sourcing the environment: From the root of the Richie repository, open the script env/setups/vitis_hls_vision.sh and define:

  • vitis_install_path: Environment variable, including the path to the Vitis build directory, e.g., “export vitis_install_path=some/path/Vitis/2022.2”.

  • opencv_install_path: Environment variable, including the path to your OpenCV directory, e.g., “export opencv_install_path=some/path/opencv”.

Then, execute source env/richie_user_setup.sh at the root of the Richie repository and select the development environment vitis_hls_vision.

5.2.2. FPGA Development #

Xilinx ZCU102

Description: A complete Linux environment with kernel and the base root filesystem for the ARMv8 host on the Xilinx Zynq UltraScale+ MPSoC ZCU102.
Tool: Vivado 2019.2.

5.2.3. Simulation #

RTL Simulation

Description: RTL simulation environment.
Tool: QuestaSim 10.6 (or 10.5).

Contents