8. Bibliography & References#
8.1. Publications#
If you use Richie in your work, you can cite one of our works:
Gianluca Bellocchi, Alessandro Capotondi, Luca Benini, and Andrea Marongiu. Richie: a framework for agile design and exploration of risc-v-based accelerator-rich heterogeneous socs. In Under-review.
Gianluca Bellocchi, Alessandro Capotondi, Francesco Conti, and Andrea Marongiu. A risc-v-based fpga overlay to simplify embedded accelerator deployment. In 2021 24th Euromicro Conference on Digital System Design (DSD), 9–17. IEEE, 2021.
8.2. Workshops & Posters#
A System-Level Design Methodology for RISC-V Accelerator-Rich SoCs (18th HiPEAC Workshop on Reconfigurable Computing (WRC), Technical University of Munich (TUM), Munich, Germany, 2024) Program
An Open-source Design Methodology for the Design Space Exploration of Accelerator-Rich Embedded Systems (7th Italian Workshops on Embedded Systems (IWES), Politecnico di Bari, Italy, 2022) Program
Richie: A Framework for Agile Design and Exploration of RISC-V Accelerator-Rich Heterogenous SoC (19th International Summer School on Advanced Computer Architecture and Compilation for High-performance Embedded Systems (ACACES), Fiuggi, Italy, 2023) Program
8.3. Additional Readings#
Additional work which can be found in or contributed to the project, or that fits in the context of Richie.
Andreas Kurth, Alessandro Capotondi, Pirmin Vogel, Luca Benini, and Andrea Marongiu. Hero: an open-source research platform for hw/sw exploration of heterogeneous manycore systems. In Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, 1–6. 2018.
Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, and Luca Benini. Pulp: a parallel ultra low power platform for next generation iot applications. In 2015 IEEE Hot Chips 27 Symposium (HCS), 1–39. IEEE Computer Society, 2015.
Francesco Conti, Pasquale Davide Schiavone, and Luca Benini. Xnor neural engine: a hardware accelerator ip for 21.6-fj/op binary neural network inference. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(11):2940–2951, 2018.